| podobné slovo | definícia |
asynchronous transfer mode
(msas) | Asynchronous Transfer Mode
- ATM |
asynchronous transfer mode
(msasasci) | Asynchronous Transfer Mode
- ATM |
asynchronous
(encz) | asynchronous,asynchronní adj: Zdeněk Brož |
asynchronously
(encz) | asynchronously,asynchronně adv: Zdeněk Brož |
asynchronous generator
(gcide) | Induction generator \In*duc"tion gen"er*a`tor\
A machine built as an induction motor and driven above
synchronous speed, thus acting as an alternating-current
generator; -- called also asynchronous generator. Below
synchronism the machine takes in electrical energy and acts
as an induction motor; at synchronism the power component of
current becomes zero and changes sign, so that above
synchronism the machine (driven for this purpose by
mechanical power) gives out electrical energy as a generator.
[Webster 1913 Suppl.] |
asynchronous
(wn) | asynchronous
adj 1: (digital communication) pertaining to a transmission
technique that does not require a common clock between
the communicating devices; timing signals are derived
from special characters in the data stream itself [ant:
synchronous]
2: not synchronous; not occurring or existing at the same time
or having the same period or phase [ant: synchronal,
synchronic, synchronous] |
asynchronous operation
(wn) | asynchronous operation
n 1: operations that occur without a regular or predictable time
relation to other events [ant: synchronous operation] |
asynchronous transfer mode
(wn) | asynchronous transfer mode
n 1: a means of digital communications that is capable of very
high speeds; suitable for transmission of images or voice
or video as well as data; "ATM is used for both LAN and
WAN" [syn: asynchronous transfer mode, ATM] |
asynchronous
(foldoc) | asynchronous
Not synchronised by a shared signal such as
clock or semaphore, proceeding independently.
Opposite: synchronous.
1. A process in a multitasking system
whose execution can proceed independently, "in the
background". Other processes may be started before the
asynchronous process has finished.
2. A communications system in which data
transmission may start at any time and is indicated by a
start bit, e.g. EIA-232. A data byte (or other element
defined by the protocol) ends with a stop bit. A
continuous marking condition (identical to stop bits but not
quantized in time), is then maintained until data resumes.
(1995-12-08)
|
asynchronous balanced mode
(foldoc) | Asynchronous Balanced Mode
ABM
A communication mode of HDLC and derivative
protocols, supporting peer-oriented point-to-point
communications between two nodes, where either node can
initiate transmission.
(1997-05-07)
|
asynchronous communications interface adapter
(foldoc) | Asynchronous Communications Interface Adapter
ACIA
(ACIA) A kind of {integrated
circuit} that provides data formatting and control to EIA-232
serial interfaces.
[Is this the same as a UART?]
(1997-05-07)
|
asynchronous logic
(foldoc) | asynchronous logic
A data-driven circuit design technique where,
instead of the components sharing a common clock and
exchanging data on clock edges, data is passed on as soon as
it is available. This removes the need to distribute a common
clock signal throughout the circuit with acceptable {clock
skew}. It also helps to reduce power dissipation in CMOS
circuits because gates only switch when they are doing
useful work rather than on every clock edge.
There are many kinds of asynchronous logic. Data signals may
use either "dual rail encoding" or "data bundling". Each dual
rail encoded Boolean is implemented as two wires. This
allows the value and the timing information to be communicated
for each data bit. Bundled data has one wire for each data
bit and another for timing. Level sensitive circuits
typically represent a logic one by a high voltage and a logic
zero by a low voltage whereas transition signalling uses a
change in the signal level to convey information. A speed
independent design is tolerant to variations in gate speeds
but not to propagation delays in wires; a delay insensitive
circuit is tolerant to variations in wire delays as well.
The purest form of circuit is delay-insensitive and uses
dual-rail encoding with transition signalling. A transition
on one wire indicates the arrival of a zero, a transition on
the other the arrival of a one. The levels on the wires are
of no significance. Such an approach enables the design of
fully delay-insensitive circuits and automatic layout as the
delays introduced by the layout compiler can't affect the
functionality (only the performance). Level sensitive designs
can use simpler, stateless logic gates but require a "return
to zero" phase in each transition.
(http://cs.man.ac.uk/amulet/async/).
(1995-01-18)
|
asynchronous transfer mode
(foldoc) | Asynchronous Transfer Mode
ATMP
Fast Packet
(ATM, or "fast packet", "Asynchronous Transfer Mode
Protocol", ATMP) A network protocol that dynamically allocates
bandwidth between incoming channels and multiplexes them onto a
stream of fixed 53-byte packets (called "cells"). A
fixed-size packet simplifies switching and multiplexing. ATM is a
connection-oriented protocol. It can use different {physical
layer} transports including SONET, DS3, fiber or {twisted
pair}.
The ATM Forum is one of the main bodies promoting ATM.
Wideband ATM is an enhancement.
{ATM acronyms
(http://atmforum.com/atmforum/acronym_index.html)}.
{Indiana acronyms
(http://cell-relay.indiana.edu/cell-relay/FAQ/ATM-Acronyms.html)}.
[More detail? Data rate(s)?]
(1996-04-01)
|
universal asynchronous receiver/transmitter
(foldoc) | Universal Asynchronous Receiver/Transmitter
Serial Communications Interface
serial IO chip
UART
(UART) An integrated circuit used
for serial communications, containing a transmitter
(parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The parallel side of a UART is usually connected to the bus
of a computer. When the computer writes a byte to the UART's
transmit data register (TDR), the UART will start to transmit
it on the serial line. The UART's status register contains a
flag bit which the computer can read to see if the UART is
ready to transmit another byte. Another status register bit
says whether the UART has received a byte from the {serial
line}, in which case the computer should read it from the
receive data register (RDR). If another byte is received
before the previous one is read, the UART will signal an
"overrun" error via another status bit.
The UART may be set up to interrupt the computer when data
is received or when ready to transmit more data.
The UART's serial connections usually go via separate {line
driver} and line receiver integrated circuits which
provide the power and voltages required to drive the serial
line and give some protection against noise on the line.
Data on the serial line is formatted by the UART according
to the setting of the UART's control register. This may also
determine the transmit and receive baud rates if the UART
contains its own clock circuits or "baud rate generators".
If incorrectly formated data is received the UART may signal a
"framing error" or "parity error".
Often the clock will run at 16 times the baud rate (bits per
second) to allow the receiver to do centre sampling - i.e. to
read each bit in the middle of its allotted time period. This
makes the UART more tolerant to variations in the clock rate
("jitter") of the incoming data.
An example of a late 1980s UART was the Intel 8450. In the
1990s, newer UARTs were developed with on-chip buffers.
This allowed higher transmission speed without data loss and
without requiring such frequent attention from the computer.
For example, the Intel 16550 has a 16 byte FIFO.
Variants include the 16C550, 16C650, 16C750, and
16C850.
The term "Serial Communications Interface" (SCI) was first
used at Motorola around 1975 to refer to their start-stop
asyncronous serial interface device, which others were calling
a UART.
See also bit bang.
[Is this the same as an ACIA?]
(2003-07-13)
|