| podobné slovo | definícia |
asynchronous transfer mode
(msas) | Asynchronous Transfer Mode
- ATM |
asynchronous transfer mode
(msasasci) | Asynchronous Transfer Mode
- ATM |
asynchronous
(encz) | asynchronous,asynchronní adj: Zdeněk Brož |
asynchronously
(encz) | asynchronously,asynchronně adv: Zdeněk Brož |
geosynchronous
(encz) | geosynchronous, |
geosynchronous orbit
(encz) | geosynchronous orbit, n: |
nonsynchronous
(encz) | nonsynchronous,nesynchronní |
synchronous converter
(encz) | synchronous converter, n: |
synchronous motor
(encz) | synchronous motor, n: |
synchronous operation
(encz) | synchronous operation, n: |
synchronously
(encz) | synchronously,synchronně adv: Zdeněk Brož |
unsynchronous
(encz) | unsynchronous, adj: |
geosynchronous orbit
(czen) | Geosynchronous Orbit,GEO[zkr.] [voj.] Zdeněk Brož a automatický překlad |
synchronous optical network
(czen) | Synchronous Optical Network,SONET[zkr.] [voj.] Zdeněk Brož a
automatický překlad |
Asynchronous
(gcide) | Asynchronous \A*syn"chro*nous\, a. [Gr. ? not + synchronous.]
Not simultaneous; not concurrent in time; -- opposed to
synchronous.
Syn: nonsynchronous, unsynchronized, unsynchronous.
[Webster 1913 Suppl.]
2. (Paleontology) occurring in different geologic times; --
of taxa/ synchronous
Syn: allochronic
[WordNet 1.5 +PJC]
3. chronologically misplaced; belonging to a different time
or era
Syn: anachronic, anachronous, anachronistic
[WordNet 1.5 +PJC]
4. (Computers) occurring at different speeds in different
computers connected by a data transmission link; -- said
of methods data of transmission between computers.
Opposite of synchronous.
[PJC] |
asynchronous generator
(gcide) | Induction generator \In*duc"tion gen"er*a`tor\
A machine built as an induction motor and driven above
synchronous speed, thus acting as an alternating-current
generator; -- called also asynchronous generator. Below
synchronism the machine takes in electrical energy and acts
as an induction motor; at synchronism the power component of
current becomes zero and changes sign, so that above
synchronism the machine (driven for this purpose by
mechanical power) gives out electrical energy as a generator.
[Webster 1913 Suppl.] |
Synchronous
(gcide) | Synchronous \Syn"chro*nous\, a. [Gr. ?; sy`n with + ? time. Cf.
Chronicle.]
Happening at the same time; simultaneous. --
Syn"chro*nous*ly, adv.
[1913 Webster] |
Synchronously
(gcide) | Synchronous \Syn"chro*nous\, a. [Gr. ?; sy`n with + ? time. Cf.
Chronicle.]
Happening at the same time; simultaneous. --
Syn"chro*nous*ly, adv.
[1913 Webster] |
asynchronous
(wn) | asynchronous
adj 1: (digital communication) pertaining to a transmission
technique that does not require a common clock between
the communicating devices; timing signals are derived
from special characters in the data stream itself [ant:
synchronous]
2: not synchronous; not occurring or existing at the same time
or having the same period or phase [ant: synchronal,
synchronic, synchronous] |
asynchronous operation
(wn) | asynchronous operation
n 1: operations that occur without a regular or predictable time
relation to other events [ant: synchronous operation] |
asynchronous transfer mode
(wn) | asynchronous transfer mode
n 1: a means of digital communications that is capable of very
high speeds; suitable for transmission of images or voice
or video as well as data; "ATM is used for both LAN and
WAN" [syn: asynchronous transfer mode, ATM] |
geosynchronous
(wn) | geosynchronous
adj 1: of or having an orbit with a fixed period of 24 hours
(although the position in the orbit may not be fixed with
respect to the earth) |
geosynchronous orbit
(wn) | geosynchronous orbit
n 1: a circular orbit around the Earth having a period of 24
hours |
nonsynchronous
(wn) | nonsynchronous
adj 1: not occurring together [syn: nonsynchronous,
unsynchronized, unsynchronised, unsynchronous] |
synchronous converter
(wn) | synchronous converter
n 1: electrical converter consisting of a synchronous machine
that converts alternating to direct current or vice versa
[syn: synchronous converter, rotary, {rotary
converter}] |
synchronous motor
(wn) | synchronous motor
n 1: electric motor in which the speed of rotation is
proportional to the frequency of the A.C. power |
synchronous operation
(wn) | synchronous operation
n 1: operations that are initiated predictably by a clock [ant:
asynchronous operation] |
synchronously
(wn) | synchronously
adv 1: in synchrony; in a synchronous manner; "in four-chambered
hearts, the two auricles move synchronously" |
unsynchronous
(wn) | unsynchronous
adj 1: not occurring together [syn: nonsynchronous,
unsynchronized, unsynchronised, unsynchronous] |
asynchronous
(foldoc) | asynchronous
Not synchronised by a shared signal such as
clock or semaphore, proceeding independently.
Opposite: synchronous.
1. A process in a multitasking system
whose execution can proceed independently, "in the
background". Other processes may be started before the
asynchronous process has finished.
2. A communications system in which data
transmission may start at any time and is indicated by a
start bit, e.g. EIA-232. A data byte (or other element
defined by the protocol) ends with a stop bit. A
continuous marking condition (identical to stop bits but not
quantized in time), is then maintained until data resumes.
(1995-12-08)
|
asynchronous balanced mode
(foldoc) | Asynchronous Balanced Mode
ABM
A communication mode of HDLC and derivative
protocols, supporting peer-oriented point-to-point
communications between two nodes, where either node can
initiate transmission.
(1997-05-07)
|
asynchronous communications interface adapter
(foldoc) | Asynchronous Communications Interface Adapter
ACIA
(ACIA) A kind of {integrated
circuit} that provides data formatting and control to EIA-232
serial interfaces.
[Is this the same as a UART?]
(1997-05-07)
|
asynchronous logic
(foldoc) | asynchronous logic
A data-driven circuit design technique where,
instead of the components sharing a common clock and
exchanging data on clock edges, data is passed on as soon as
it is available. This removes the need to distribute a common
clock signal throughout the circuit with acceptable {clock
skew}. It also helps to reduce power dissipation in CMOS
circuits because gates only switch when they are doing
useful work rather than on every clock edge.
There are many kinds of asynchronous logic. Data signals may
use either "dual rail encoding" or "data bundling". Each dual
rail encoded Boolean is implemented as two wires. This
allows the value and the timing information to be communicated
for each data bit. Bundled data has one wire for each data
bit and another for timing. Level sensitive circuits
typically represent a logic one by a high voltage and a logic
zero by a low voltage whereas transition signalling uses a
change in the signal level to convey information. A speed
independent design is tolerant to variations in gate speeds
but not to propagation delays in wires; a delay insensitive
circuit is tolerant to variations in wire delays as well.
The purest form of circuit is delay-insensitive and uses
dual-rail encoding with transition signalling. A transition
on one wire indicates the arrival of a zero, a transition on
the other the arrival of a one. The levels on the wires are
of no significance. Such an approach enables the design of
fully delay-insensitive circuits and automatic layout as the
delays introduced by the layout compiler can't affect the
functionality (only the performance). Level sensitive designs
can use simpler, stateless logic gates but require a "return
to zero" phase in each transition.
(http://cs.man.ac.uk/amulet/async/).
(1995-01-18)
|
asynchronous transfer mode
(foldoc) | Asynchronous Transfer Mode
ATMP
Fast Packet
(ATM, or "fast packet", "Asynchronous Transfer Mode
Protocol", ATMP) A network protocol that dynamically allocates
bandwidth between incoming channels and multiplexes them onto a
stream of fixed 53-byte packets (called "cells"). A
fixed-size packet simplifies switching and multiplexing. ATM is a
connection-oriented protocol. It can use different {physical
layer} transports including SONET, DS3, fiber or {twisted
pair}.
The ATM Forum is one of the main bodies promoting ATM.
Wideband ATM is an enhancement.
{ATM acronyms
(http://atmforum.com/atmforum/acronym_index.html)}.
{Indiana acronyms
(http://cell-relay.indiana.edu/cell-relay/FAQ/ATM-Acronyms.html)}.
[More detail? Data rate(s)?]
(1996-04-01)
|
binary synchronous transmission
(foldoc) | Binary Synchronous Transmission
2780
3780
bisync
(Bisynch) An IBM link protocol, developed in
the 1960 and popular in the 1970s and 1980s.
Binary Synchronous Transmission has been largely replaced in
IBM environments with SDLC. Bisync was developed for
batch communications between a System 360 computer and the
IBM 2780 and 3780 Remote Job Entry (RJE) terminals. It
supports RJE and on-line terminals in the CICS/VSE
environment. It operates with EBCDIC or ASCII {character
sets}. It requires that every message be acknowledged (ACK)
or negatively acknowledged (NACK) so it has high
transmission overhead. It is typically character oriented and
half-duplex, although some of the bisync protocol flavours
or dialects support binary transmission and full-duplex
operation.
(1997-01-07)
|
double data rate synchronous random access memory
(foldoc) | Double Data Rate Random Access Memory
DDR
DDR-RAM
DDR-SDRAM
Double Data Rate Synchronous Random Access Memory
(DDR-RAM, DDR-SDRAM ...Synchronous...) RAM that
transfers data on both 0-1 and 1-0 clock transitions,
theoretically yielding twice the data transfer rate of normal
RAM or SDRAM.
{DDR-RAM Article
(http://pcreview.co.uk/Article.php?aid=9)}.
{DDR-SDRAM Article
(http://www4.tomshardware.com/mainboard/00q4/001030/)}.
(2001-05-24)
|
single data rate synchronous dynamic random access memory
(foldoc) | Single Data Rate Random Access Memory
SDR-RAM
SDR-SDRAM
Single Data Rate Synchronous Dynamic Random Access Memory
(SDR-RAM, SDR-SDRAM, Single Data Rate Synchronous
Dynamic Random Access Memory) RAM or SDRAM that transfers
data on only one clock transition (0-1 or 1-0), in contrast
to DDR-RAM.
(2001-05-24)
|
synchronous data link control
(foldoc) | Synchronous Data Link Control
(SDLC) An IBM protocol.
A discipline conforming to subsets of the ADCCP of ANSI
and the HDLC of the {International Organization for
Standardization}. SDLC manages synchronous, code-transparent,
bit-serial communication which can be duplex or
half-duplex; switched or non-switched; point-to-point,
multipoint, or loop.
Compare Binary Synchronous Communication.
(1995-03-22)
|
synchronous digital hierarchy
(foldoc) | Synchronous Digital Hierarchy
SDH
(SDH) An international digital
telecommunications network hierarchy which standardises
transmission around the bit rate of 51.84 megabits per second,
which is also called STS-1. Multiples of this bit rate
comprise higher bit rate streams. Thus STS-3 is 3 times
STS-1, STS-12 is 12 times STS-1, and so on. STS-3 is the
lowest bit rate expected to carry ATM traffic, and is also
referred to as STM-1 (Synchronous Transport Module-Level 1).
The SDH specifies how payload data is framed and transported
synchronously across optical fibre transmission links without
requiring all the links and nodes to have the same
synchronized clock for data transmission and recovery
(i.e. both the clock frequency and phase are allowed to have
variations, or be plesiochronous).
SDH offers several advantages over the current multiplexing
technology, which is known as {Plesiochronous Digital
Hierarchy}. Where PDH lacks built-in facilities for automatic
management and routing, and locks users into proprietary
methods, SDH can improve network reliability and performance,
offers much greater flexibility and lower operating and
maintenance costs, and provides for a faster provision of new
services.
Under SDH, incoming traffic is synchronized and enhanced with
network management bits before being multiplexed into the
STM-1 fixed rate frame.
The fundamental clock frequency around which the SDH or
SONET framing is done is 8 KHz or 125 microseconds.
SONET (Synchronous Optical Network) is the American version
of SDH.
(1995-03-02)
|
synchronous dram
(foldoc) | Synchronous Dynamic Random Access Memory
SDRAM
Synchronous DRAM
(SDRAM, Synchronous DRAM) A form of DRAM which
adds a separate clock signal to the control signals. SDRAM
chips can contain more complex state machines, allowing them
to support "burst" access modes that clock out a series of
successive bits (similar to the nibble mode DRAM).
(2007-05-08)
|
synchronous dynamic random access memory
(foldoc) | Synchronous Dynamic Random Access Memory
SDRAM
Synchronous DRAM
(SDRAM, Synchronous DRAM) A form of DRAM which
adds a separate clock signal to the control signals. SDRAM
chips can contain more complex state machines, allowing them
to support "burst" access modes that clock out a series of
successive bits (similar to the nibble mode DRAM).
(2007-05-08)
|
synchronous graphics ram
(foldoc) | Synchronous Graphics Random Access Memory
SGRAM
Synchronous Graphics RAM
(SGRAM, Synchronous Graphics RAM) A type of
Synchronous DRAM optimised for use in graphics hardware.
Extra features can include burst operation, block write
and write per bit. SGRAMs are designed to provide the very
high throughput needed for graphics-intensive operations
such as 3d rendering and full-motion video.
(1996-11-28)
|
synchronous graphics random access memory
(foldoc) | Synchronous Graphics Random Access Memory
SGRAM
Synchronous Graphics RAM
(SGRAM, Synchronous Graphics RAM) A type of
Synchronous DRAM optimised for use in graphics hardware.
Extra features can include burst operation, block write
and write per bit. SGRAMs are designed to provide the very
high throughput needed for graphics-intensive operations
such as 3d rendering and full-motion video.
(1996-11-28)
|
synchronous idle
(foldoc) | Synchronous idle
(SYN) The mnemonic for ASCII character 22.
[Why?]
(1996-06-28)
|
synchronous key encryption
(foldoc) | synchronous key encryption
Data encryption using two
interlocking keys where enything encoded using one key may be
decoded using the other key. This means if someone makes one
of the two keys publicly available (as in {public-key
encryption}) and keeps the other private, then anyone may send
them a message or data that only they can decode, giving
privacy, and furthermore, the sender may also encrypt that
same message additionally with their own private key, making
it impossible to read without decoding first with *their*
__public__ key by the receiver, this gives authenticity.
It is a very powerful system. One cannot determine one key
from the other, nor can they crack the encryption by computing
all combinations, because, depending on the size of the keys
(sometimes as large as 1024 bytes, though having grown from
smaller versions in popular implementations of the software
which does this), the amount of computing power required to
crack the code is unavailable, even supercomputers would take
more than a hundred years to crack it.
PGP is a publicly availble software implementation written
by Phil Zimmermann.
(1994-10-10)
|
synchronous optical network
(foldoc) | Synchronous Optical NETwork
SONET
(SONET) A broadband networking standard based
on point-to-point optical fibre networks. SONET will
provide a high-bandwidth "pipe" to support ATM-based
services.
The SONET standard will establish a digital {hierarchical
network} with a consistent worldwide transport scheme. SONET
has been designed to take advantage of fibre, in contrast to
the plain old telephone system which was designed for copper
wires.
SONET carries circuit-switched data in frames at speeds in
multiples of 51.84 megabits per second (Mbps) up to 48 * 51.84
Mbps = 2.488 gigabits per second. Since SONET uses multiple
channels to transmit data, each SONET frame can be
considered to be a two-dimensional table of bytes that is 9
rows high and 90 columns deep. For every OC-n level, SONET
can transmit n number of frames at a given time. Groups of
frames are called superframes.
SONET is the American version of SDH.
[Wulf Losee; Corporate Computing 8.92; STACKS; LAN Magazine
10.93].
(1994-11-30)
|
universal asynchronous receiver/transmitter
(foldoc) | Universal Asynchronous Receiver/Transmitter
Serial Communications Interface
serial IO chip
UART
(UART) An integrated circuit used
for serial communications, containing a transmitter
(parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The parallel side of a UART is usually connected to the bus
of a computer. When the computer writes a byte to the UART's
transmit data register (TDR), the UART will start to transmit
it on the serial line. The UART's status register contains a
flag bit which the computer can read to see if the UART is
ready to transmit another byte. Another status register bit
says whether the UART has received a byte from the {serial
line}, in which case the computer should read it from the
receive data register (RDR). If another byte is received
before the previous one is read, the UART will signal an
"overrun" error via another status bit.
The UART may be set up to interrupt the computer when data
is received or when ready to transmit more data.
The UART's serial connections usually go via separate {line
driver} and line receiver integrated circuits which
provide the power and voltages required to drive the serial
line and give some protection against noise on the line.
Data on the serial line is formatted by the UART according
to the setting of the UART's control register. This may also
determine the transmit and receive baud rates if the UART
contains its own clock circuits or "baud rate generators".
If incorrectly formated data is received the UART may signal a
"framing error" or "parity error".
Often the clock will run at 16 times the baud rate (bits per
second) to allow the receiver to do centre sampling - i.e. to
read each bit in the middle of its allotted time period. This
makes the UART more tolerant to variations in the clock rate
("jitter") of the incoming data.
An example of a late 1980s UART was the Intel 8450. In the
1990s, newer UARTs were developed with on-chip buffers.
This allowed higher transmission speed without data loss and
without requiring such frequent attention from the computer.
For example, the Intel 16550 has a 16 byte FIFO.
Variants include the 16C550, 16C650, 16C750, and
16C850.
The term "Serial Communications Interface" (SCI) was first
used at Motorola around 1975 to refer to their start-stop
asyncronous serial interface device, which others were calling
a UART.
See also bit bang.
[Is this the same as an ACIA?]
(2003-07-13)
|