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addressing mode
(foldoc) | addressing mode
1. One of a set of methods for
specifying the operand(s) for a machine code
instruction. Different processors vary greatly in the
number of addressing modes they provide. The more complex
modes described below can usually be replaced with a short
sequence of instructions using only simpler modes.
The most common modes are "register" - the operand is stored
in a specified register; "absolute" - the operand is stored
at a specified memory address; and "immediate" - the operand
is contained within the instruction.
Most processors also have indirect addressing modes, e.g.
"register indirect", "memory indirect" where the specified
register or memory location does not contain the operand but
contains its address, known as the "effective address". For
an absolute addressing mode, the effective address is
contained within the instruction.
Indirect addressing modes often have options for pre- or post-
increment or decrement, meaning that the register or memory
location containing the effective address is incremented or
decremented by some amount (either fixed or also specified in
the instruction), either before or after the instruction is
executed. These are very useful for stacks and for
accessing blocks of data. Other variations form the effective
address by adding together one or more registers and one or
more constants which may themselves be direct or indirect.
Such complex addressing modes are designed to support access
to multidimensional arrays and arrays of data structures.
The addressing mode may be "implicit" - the location of the
operand is obvious from the particular instruction. This
would be the case for an instruction that modified a
particular control register in the CPU or, in a stack based
processor where operands are always on the top of the stack.
2. In IBM System 370/XA the addressing mode bit controls
the size of the effective address generated. When this bit
is zero, the CPU is in the 24-bit addressing mode, and 24 bit
instruction and operand effective addresses are generated.
When this bit is one, the CPU is in the 31-bit addressing
mode, and 31-bit instruction and operand effective addresses
are generated.
["IBM System/370 Extended Architecture Principles of
Operation", Chapter 5., 'Address Generation', BiModal
Addressing].
(1995-03-30)
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