| slovo | definícia |
flip-flop
(encz) | flip-flop,přemet vzad Zdeněk Brož |
flip-flop
(wn) | flip-flop
n 1: a decision to reverse an earlier decision [syn: reversal,
change of mind, flip-flop, turnabout, turnaround]
2: a backless sandal held to the foot by a thong between the big
toe and the second toe [syn: flip-flop, thong]
3: an electronic circuit that can assume either of two stable
states
4: a backward somersault
v 1: reverse (a direction, attitude, or course of action) [syn:
interchange, tack, switch, alternate, flip,
flip-flop] |
flip-flop
(foldoc) | flip-flop
Eccles-Jordan circuit
A digital logic circuit that can be in one of two
states which it switches (or "toggles") between under
control of its inputs. It can thus be considered as a one bit
memory. Three types of flip-flop are common: the {SR
flip-flop}, the JK flip-flop and the D-type flip-flop (or
latch).
Early literature refers to the "Eccles-Jordan circuit" and the
"Eccles-Jordan binary counter", using two vacuum tubes as
the active (amplifying) elements for each bit of information
storage. Later implementations using bipolar transistors
could operate at up to 20 million state transitions per second
as early as 1963.
(1995-11-11)
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| | podobné slovo | definícia |
flip-flops
(encz) | flip-flops,žabky n: letní otevřená obuv xkomczax |
d-type flip-flop
(foldoc) | D-type flip-flop
A digital logic device that stores the status of
its "D" input whenever its clock input makes a certain
transition (low to high or high to low). The output, "Q",
shows the currently stored value.
Compare J-K flip-flop.
(1995-03-28)
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jk flip-flop
(foldoc) | JK flip-flop
An edge triggered SR flip-flop with extra logic
such that only one of the R and S inputs is enabled at any
time. This prevents a race condition which can occur when
both inputs of an RS flip-flop are active at the same time.
In a JK flip-flop the R and S inputs are renamed J and K. The
set input (J) is only enabled when the flip-flop is reset and
K when it is set.
If both J and K inputs are held active then the outputs will
change ("togle") on each falling edge of the clock. JK
flip-flops can be used to build a binary counter with a
reset input.
(http://play-hookey.com/digital/logic7.html).
[Was it named after Jack Kilby?]
(2004-07-17)
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rs flip-flop
(foldoc) | SR flip-flop
RS flip-flop
(Or "RS flip-flop") A "set/reset" flip-flop in
which activating the "S" input will switch it to one stable
state and activating the "R" input will switch it to the other
state.
The outputs of a basic SR flip-flop change whenever its R or S
inputs change appropriately. A clocked SR flip-flop has an
extra clock input which enables or disables the other two
inputs. When they are disabled the outputs remain constant.
If we connect two clocked SR flip-flops so that the Q and /Q
outputs of the first, "master" flip-flop drive the S and R
inputs of the second, "slave" flip-flop, and we drive the
slave's clock input with an inverted version of the master's
clock, then we have an edge-triggered RS flip-flop. The
external R and S inputs of this device are latched on one edge
(transition) of the clock (e.g. the falling edge) and the
outputs will only change on the next opposite (rising) edge.
If both R and S inputs are active (when enabled), a {race
condition} occurs and the outputs will be in an indeterminate
state. A JK flip-flop avoids this possibility.
(http://play-hookey.com/digital/logic4.html).
(1997-05-15)
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sr flip-flop
(foldoc) | SR flip-flop
RS flip-flop
(Or "RS flip-flop") A "set/reset" flip-flop in
which activating the "S" input will switch it to one stable
state and activating the "R" input will switch it to the other
state.
The outputs of a basic SR flip-flop change whenever its R or S
inputs change appropriately. A clocked SR flip-flop has an
extra clock input which enables or disables the other two
inputs. When they are disabled the outputs remain constant.
If we connect two clocked SR flip-flops so that the Q and /Q
outputs of the first, "master" flip-flop drive the S and R
inputs of the second, "slave" flip-flop, and we drive the
slave's clock input with an inverted version of the master's
clock, then we have an edge-triggered RS flip-flop. The
external R and S inputs of this device are latched on one edge
(transition) of the clock (e.g. the falling edge) and the
outputs will only change on the next opposite (rising) edge.
If both R and S inputs are active (when enabled), a {race
condition} occurs and the outputs will be in an indeterminate
state. A JK flip-flop avoids this possibility.
(http://play-hookey.com/digital/logic4.html).
(1997-05-15)
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