| slovo | definícia |
scan design
(foldoc) | scan design
Scan-In, Scan-Out
(Or "Scan-In, Scan-Out") A electronic circuit
design technique which aims to increase the controllability
and observability of a digital logic circuit by
incorporating special "scan registers" into the circuit so
that they form a scan path.
Some of the more common types of scan design include the
multiplexed register designs and {level-sensitive scan
design} (LSSD) used extensively by IBM. Boundary scan can
be used alone or in combination with either of the above
techniques.
["Digital Systems Testing and Testable Design" by Abramovici,
Breuer, and Friedman, ISBN 0-7167-8179-4].
["Design of Testable Logic Circuits" by R.G. Bennetts,
(Brunel/Southhampton Universities), ISBN 0-201-14403-4].
(1995-02-23)
|
| | podobné slovo | definícia |
level-sensitive scan design
(foldoc) | level-sensitive scan design
LSSD
(circuit design) (LSSD) A kind of scan design which uses
separate system and scan clocks to distinguish between normal
and test mode. Latches are used in pairs, each has a normal
data input, data output and clock for system operation. For
test operation, the two latches form a master/slave pair with
one scan input, one scan output and non-overlapping scan
clocks A and B which are held low during system operation but
cause the scan data to be latched when pulsed high during
scan.
____
| |
Sin ----|S |
A ------|> |
| Q|---+--------------- Q1
D1 -----|D | |
CLK1 ---|> | |
|____| | ____
| | |
+---|S |
B -------------------|> |
| Q|------ Q2 / SOut
D2 ------------------|D |
CLK2 ----------------|> |
|____|
In a single latch LSSD configuration, the second latch is used
only for scan operation. Allowing it to be use as a second
system latch reduces the silicon overhead.
(1995-02-15)
|
|