| slovo | definícia |
cache
(encz) | cache,cache n: Zdeněk Brož |
cache
(encz) | cache,mezipaměť n: [it.] Stanislav Horáček |
cache
(encz) | cache,rychlá vyrovnávací paměť n: [it.] Jiří Šmoldas |
cache
(encz) | cache,skrýš n: Zdeněk Brož |
cache
(encz) | cache,úkryt n: Zdeněk Brož |
cache
(czen) | cache,cachen: Zdeněk Brož |
cache
(gcide) | cache \cache\ (k[a^]sh), n. [F., a hiding place, fr. cacher to
conceal, to hide.]
1. A hole in the ground, or other hiding place, for
concealing and preserving provisions which it is
inconvenient to carry. --Kane.
[1913 Webster]
2. That which is hidden in a cache[2]; a hoard; a stockpile.
[PJC]
3. (Computers) A form of memory in a computer which has a
faster access time than most of main memory, and is
usually used to store the most frequently accessed data in
main memory during execution of a program.
[PJC] |
cache
(gcide) | cache \cache\ (k[a^]sh), v. t.
To store in a cache[1].
[PJC] Cachectic |
cache
(wn) | cache
n 1: a hidden storage space (for money or provisions or weapons)
2: a secret store of valuables or money [syn: hoard, cache,
stash]
3: (computer science) RAM memory that is set aside as a
specialized buffer storage that is continually updated; used
to optimize data transfers between system elements with
different characteristics [syn: cache, memory cache]
v 1: save up as for future use [syn: hoard, stash, cache,
lay away, hive up, squirrel away] |
cache
(foldoc) | cache
cache memory
caching
/kash/ A small fast memory holding
recently accessed data, designed to speed up subsequent access
to the same data. Most often applied to processor-memory
access but also used for a local copy of data accessible over
a network etc.
When data is read from, or written to, main memory a copy is
also saved in the cache, along with the associated main memory
address. The cache monitors addresses of subsequent reads to
see if the required data is already in the cache. If it is (a
cache hit) then it is returned immediately and the main
memory read is aborted (or not started). If the data is not
cached (a cache miss) then it is fetched from main memory
and also saved in the cache.
The cache is built from faster memory chips than main memory
so a cache hit takes much less time to complete than a normal
memory access. The cache may be located on the same
integrated circuit as the CPU, in order to further reduce
the access time. In this case it is often known as {primary
cache} since there may be a larger, slower secondary cache
outside the CPU chip.
The most important characteristic of a cache is its hit rate
- the fraction of all memory accesses which are satisfied from
the cache. This in turn depends on the cache design but
mostly on its size relative to the main memory. The size is
limited by the cost of fast memory chips.
The hit rate also depends on the access pattern of the
particular program being run (the sequence of addresses being
read and written). Caches rely on two properties of the
access patterns of most programs: temporal locality - if
something is accessed once, it is likely to be accessed again
soon, and spatial locality - if one memory location is
accessed then nearby memory locations are also likely to be
accessed. In order to exploit spatial locality, caches often
operate on several words at a time, a "cache line" or "cache
block". Main memory reads and writes are whole cache lines.
When the processor wants to write to main memory, the data is
first written to the cache on the assumption that the
processor will probably read it again soon. Various different
policies are used. In a write-through cache, data is
written to main memory at the same time as it is cached. In a
write-back cache it is only written to main memory when it
is forced out of the cache.
If all accesses were writes then, with a write-through policy,
every write to the cache would necessitate a main memory
write, thus slowing the system down to main memory speed.
However, statistically, most accesses are reads and most of
these will be satisfied from the cache. Write-through is
simpler than write-back because an entry that is to be
replaced can just be overwritten in the cache as it will
already have been copied to main memory whereas write-back
requires the cache to initiate a main memory write of the
flushed entry followed (for a processor read) by a main memory
read. However, write-back is more efficient because an entry
may be written many times in the cache without a main memory
access.
When the cache is full and it is desired to cache another line
of data then a cache entry is selected to be written back to
main memory or "flushed". The new line is then put in its
place. Which entry is chosen to be flushed is determined by a
"replacement algorithm".
Some processors have separate instruction and data caches.
Both can be active at the same time, allowing an instruction
fetch to overlap with a data read or write. This separation
also avoids the possibility of bad cache conflict between
say the instructions in a loop and some data in an array which
is accessed by that loop.
See also direct mapped cache, fully associative cache,
sector mapping, set associative cache.
(1997-06-25)
|
| | podobné slovo | definícia |
cachectic
(encz) | cachectic,kachektický adj: Zdeněk Brožcachectic,sešlý adj: Zdeněk Brož |
cached
(encz) | cached,uloženo v rychlé vyrovnávací paměti adj: [it.] Jiří Šmoldas |
caches
(encz) | caches,skrýše n: Zdeněk Brož |
cachet
(encz) | cachet,prestiž n: macskacachet,značka n: macska |
cachexia
(encz) | cachexia,kachexie n: Zdeněk Brožcachexia,sešlost n: Zdeněk Brož |
cachexy
(encz) | cachexy,kachexie n: Zdeněk Brož |
disk cache
(encz) | disk cache, n: |
food cache
(encz) | food cache, n: |
lettre de cachet
(encz) | lettre de cachet, n: |
memory cache
(encz) | memory cache, n: |
Cachectic
(gcide) | Cachectic \Ca*chec"tic\, Cachectical \Ca*chec"tic*al\, a. [L.
cachecticus, Gr. ?????????: cf. F. cachectique.]
Having, or pertaining to, cachexia; as, cachectic remedies;
cachectical blood. --Arbuthnot.
[1913 Webster] |
Cachectical
(gcide) | Cachectic \Ca*chec"tic\, Cachectical \Ca*chec"tic*al\, a. [L.
cachecticus, Gr. ?????????: cf. F. cachectique.]
Having, or pertaining to, cachexia; as, cachectic remedies;
cachectical blood. --Arbuthnot.
[1913 Webster] |
Cachemia
(gcide) | Cachaemia \Ca*ch[ae]"mi*a\, Cachemia \Ca*che"mi*a\, n. [NL., fr.
Gr. ? bad + ? blood.] (Med.)
A degenerated or poisoned condition of the blood. --
Ca*ch[ae]"mic, Ca*che"mic, a.
[Webster 1913 Suppl.] |
Cachemic
(gcide) | Cachaemia \Ca*ch[ae]"mi*a\, Cachemia \Ca*che"mi*a\, n. [NL., fr.
Gr. ? bad + ? blood.] (Med.)
A degenerated or poisoned condition of the blood. --
Ca*ch[ae]"mic, Ca*che"mic, a.
[Webster 1913 Suppl.] |
Cachepot
(gcide) | Cachepot \Cache`pot"\ (k[.a]sh`p[-o]"), n. [F., fr. cacher to
hide + pot a pot.]
An ornamental casing for a flowerpot, of porcelain, metal,
paper, etc.
[1913 Webster] |
Cachet
(gcide) | Cachet \Cach"et\, n. [F. fr. cacher to hide.]
A seal, as of a letter.
[1913 Webster]
Lettre de cachet [F.], a sealed letter, especially a letter
or missive emanating from the sovereign; -- much used in
France before the Revolution as an arbitrary order of
imprisonment.
[1913 Webster] Cachexia |
Cachexia
(gcide) | Cachexia \Ca*chex"i*a\, Cachexy \Ca*chex"y\, n. [L. cachexia,
Gr. kachexi`a; kako`s bad + "e`xis condition.]
A condition of ill health and impairment of nutrition due to
impoverishment of the blood, esp. when caused by a specific
morbid process (as cancer or tubercle).
[1913 Webster] |
Cachexy
(gcide) | Cachexia \Ca*chex"i*a\, Cachexy \Ca*chex"y\, n. [L. cachexia,
Gr. kachexi`a; kako`s bad + "e`xis condition.]
A condition of ill health and impairment of nutrition due to
impoverishment of the blood, esp. when caused by a specific
morbid process (as cancer or tubercle).
[1913 Webster] |
Lettre de cachet
(gcide) | Cachet \Cach"et\, n. [F. fr. cacher to hide.]
A seal, as of a letter.
[1913 Webster]
Lettre de cachet [F.], a sealed letter, especially a letter
or missive emanating from the sovereign; -- much used in
France before the Revolution as an arbitrary order of
imprisonment.
[1913 Webster] Cachexia |
cachectic
(wn) | cachectic
adj 1: relating to or having the symptoms of cachexia |
cachet
(wn) | cachet
n 1: an indication of approved or superior status [syn:
cachet, seal, seal of approval]
2: a warrant formerly issued by a French king who could warrant
imprisonment or death in a signed letter under his seal [syn:
cachet, lettre de cachet]
3: a seal on a letter |
cachexia
(wn) | cachexia
n 1: any general reduction in vitality and strength of body and
mind resulting from a debilitating chronic disease [syn:
cachexia, cachexy, wasting] |
cachexy
(wn) | cachexy
n 1: any general reduction in vitality and strength of body and
mind resulting from a debilitating chronic disease [syn:
cachexia, cachexy, wasting] |
disk cache
(wn) | disk cache
n 1: a cache that stores copies of frequently used disk sectors
in random access memory (RAM) so they can be read without
accessing the slower disk |
food cache
(wn) | food cache
n 1: food in a secure or hidden storage place |
lettre de cachet
(wn) | lettre de cachet
n 1: a warrant formerly issued by a French king who could
warrant imprisonment or death in a signed letter under his
seal [syn: cachet, lettre de cachet] |
memory cache
(wn) | memory cache
n 1: (computer science) RAM memory that is set aside as a
specialized buffer storage that is continually updated;
used to optimize data transfers between system elements
with different characteristics [syn: cache, {memory
cache}] |
backside cache
(foldoc) | backside cache
An implementation of secondary cache
memory that allows it to be directly accessed by the CPU.
Backside cache is used by Apple Computers, Inc. in their
PowerPC G3 processor. Previous PowerPC processors used the
system bus to access both secondary cache and main memory.
In the PowerPC G3 a dedicated bus handles only CPU/cache
transactions. This bus can operate faster than the system bus
thus improving the overall performance of the processor.
The term apparently derives from the relocation of the
secondary cache from the motherboard to the processor card
itself, i.e. on the backside of the processor card.
(1998-09-10)
|
cache block
(foldoc) | cache line
cache block
(Or cache block) The smallest unit of memory than
can be transferred between the main memory and the cache.
Rather than reading a single word or byte from main memory at
a time, each cache entry is usually holds a certain number of
words, known as a "cache line" or "cache block" and a whole
line is read and cached at once. This takes advantage of the
principle of locality of reference: if one location is read
then nearby locations (particularly following locations) are
likely to be read soon afterward. It can also take advantage
of page-mode DRAM which allows faster access to
consecutive locations.
(1997-01-21)
|
cache coherency
(foldoc) | cache coherency
cache consistency
(Or "cache consistency") /kash koh-heer'n-see/ The
synchronisation of data in multiple caches such that reading
a memory location via any cache will return the most recent
data written to that location via any (other) cache.
Some parallel processors do not cache accesses to {shared
memory} to avoid the issue of cache coherency. If caches are
used with shared memory then some system is required to detect
when data in one processor's cache should be discarded or
replaced because another processor has updated that memory
location. Several such schemes have been devised.
(1998-11-10)
|
cache conflict
(foldoc) | cache conflict
A sequence of accesses to memory repeatedly
overwriting the same cache entry. This can happen if two
blocks of data, which are mapped to the same set of cache
locations, are needed simultaneously.
For example, in the case of a direct mapped cache, if
arrays A, B, and C map to the same range of cache locations,
thrashing will occur when the following loop is executed:
for (i=1; i |
cache consistency
(foldoc) | cache coherency
cache consistency
(Or "cache consistency") /kash koh-heer'n-see/ The
synchronisation of data in multiple caches such that reading
a memory location via any cache will return the most recent
data written to that location via any (other) cache.
Some parallel processors do not cache accesses to {shared
memory} to avoid the issue of cache coherency. If caches are
used with shared memory then some system is required to detect
when data in one processor's cache should be discarded or
replaced because another processor has updated that memory
location. Several such schemes have been devised.
(1998-11-10)
|
cache hit
(foldoc) | cache hit
A request to read from memory which can satisfied
from the cache without using the main memory.
Opposite: cache miss.
(1997-01-21)
|
cache line
(foldoc) | cache line
cache block
(Or cache block) The smallest unit of memory than
can be transferred between the main memory and the cache.
Rather than reading a single word or byte from main memory at
a time, each cache entry is usually holds a certain number of
words, known as a "cache line" or "cache block" and a whole
line is read and cached at once. This takes advantage of the
principle of locality of reference: if one location is read
then nearby locations (particularly following locations) are
likely to be read soon afterward. It can also take advantage
of page-mode DRAM which allows faster access to
consecutive locations.
(1997-01-21)
|
cache memory
(foldoc) | cache
cache memory
caching
/kash/ A small fast memory holding
recently accessed data, designed to speed up subsequent access
to the same data. Most often applied to processor-memory
access but also used for a local copy of data accessible over
a network etc.
When data is read from, or written to, main memory a copy is
also saved in the cache, along with the associated main memory
address. The cache monitors addresses of subsequent reads to
see if the required data is already in the cache. If it is (a
cache hit) then it is returned immediately and the main
memory read is aborted (or not started). If the data is not
cached (a cache miss) then it is fetched from main memory
and also saved in the cache.
The cache is built from faster memory chips than main memory
so a cache hit takes much less time to complete than a normal
memory access. The cache may be located on the same
integrated circuit as the CPU, in order to further reduce
the access time. In this case it is often known as {primary
cache} since there may be a larger, slower secondary cache
outside the CPU chip.
The most important characteristic of a cache is its hit rate
- the fraction of all memory accesses which are satisfied from
the cache. This in turn depends on the cache design but
mostly on its size relative to the main memory. The size is
limited by the cost of fast memory chips.
The hit rate also depends on the access pattern of the
particular program being run (the sequence of addresses being
read and written). Caches rely on two properties of the
access patterns of most programs: temporal locality - if
something is accessed once, it is likely to be accessed again
soon, and spatial locality - if one memory location is
accessed then nearby memory locations are also likely to be
accessed. In order to exploit spatial locality, caches often
operate on several words at a time, a "cache line" or "cache
block". Main memory reads and writes are whole cache lines.
When the processor wants to write to main memory, the data is
first written to the cache on the assumption that the
processor will probably read it again soon. Various different
policies are used. In a write-through cache, data is
written to main memory at the same time as it is cached. In a
write-back cache it is only written to main memory when it
is forced out of the cache.
If all accesses were writes then, with a write-through policy,
every write to the cache would necessitate a main memory
write, thus slowing the system down to main memory speed.
However, statistically, most accesses are reads and most of
these will be satisfied from the cache. Write-through is
simpler than write-back because an entry that is to be
replaced can just be overwritten in the cache as it will
already have been copied to main memory whereas write-back
requires the cache to initiate a main memory write of the
flushed entry followed (for a processor read) by a main memory
read. However, write-back is more efficient because an entry
may be written many times in the cache without a main memory
access.
When the cache is full and it is desired to cache another line
of data then a cache entry is selected to be written back to
main memory or "flushed". The new line is then put in its
place. Which entry is chosen to be flushed is determined by a
"replacement algorithm".
Some processors have separate instruction and data caches.
Both can be active at the same time, allowing an instruction
fetch to overlap with a data read or write. This separation
also avoids the possibility of bad cache conflict between
say the instructions in a loop and some data in an array which
is accessed by that loop.
See also direct mapped cache, fully associative cache,
sector mapping, set associative cache.
(1997-06-25)
|
cache miss
(foldoc) | cache miss
A request to read from memory which cannot be
satisfied from the cache, for which the main memory has to
be consulted.
Opposite: cache hit.
(1997-01-21)
|
cache on a stick
(foldoc) | Cache On A STick
COAST
(COAST) Intel Corporation attempt to's
standardise the modular L2 cache subsystem in
Pentium-based computers.
A COAST module should be about 4.35" wide by 1.14" high.
According to earlier specifications from Motorola, a module
between 4.33" and 4.36" wide, and between 1.12" and 1.16" high
is within the COAST standard. Some module vendors, including
some major motherboard suppliers, greatly violate the height
specification.
Another COAST specification violated by many suppliers
concerns clock distribution in synchronous modules. The
specification requires that the clock tree to each synchronous
chip be balanced, i.e. equal length from edge of the connector
to individual chips. An unbalanced clock tree increases
reflections and noise.
For a 256 kilobyte cache module the standard requires the
same clock be used for both chips but some vendors use
separate clocks to reduce loading on the clock driver and
hence increase the clock speed. However, this creates
unbalanced loading in other motherboard configurations, such
as motherboards with soldered caches in the system.
(1996-06-10)
|
direct mapped cache
(foldoc) | direct mapped cache
A cache where the cache location for a given
address is determined from the middle address bits. If the
cache line size is 2^n then the bottom n address bits
correspond to an offset within a cache entry. If the cache
can hold 2^m entries then the next m address bits give the
cache location. The remaining top address bits are stored as
a "tag" along with the entry.
In this scheme, there is no choice of which block to flush on
a cache miss since there is only one place for any block to
go. This simple scheme has the disadvantage that if the
program alternately accesses different addresses which map to
the same cache location then it will suffer a cache miss on
every access to these locations. This kind of {cache
conflict} is quite likely on a multi-processor. See also
fully associative cache, set associative cache.
|
fully associative cache
(foldoc) | fully associative cache
A type of cache in which data from any
address can be stored in any cache location. The whole address
must be used as the tag (the value that identifies a block of data
in the cache). All tags must be compared simultaneously
(associatively) with the requested address and if one matches then
its associated data is accessed. This requires an {associative
memory} to hold the tags which makes this form of cache more
expensive. It does however solve the problem of contention for
cache locations (cache conflict) since a block need only be
flushed when the whole cache is full and then the block to flush
can be selected in a more efficient way.
The alternatives are direct mapped cache or {set associative
cache}.
(2013-08-09)
|
l1 cache
(foldoc) | primary cache
L1 cache
level 1 cache
level one cache
(L1 cache, level one cache) A small,
fast cache memory inside or close to the CPU chip.
For example, an Intel 80486 has an eight-kilobyte on-chip
cache, and most Pentiums have a 16-KB on-chip level one
cache that consists of an 8-KB instruction cache and an 8-KB
data cache.
The larger, slower secondary cache is normally connected to
the CPU via its external bus.
(1997-06-25)
|
l2 cache
(foldoc) | secondary cache
L2 cache
level 2 cache
level two cache
second level cache
(Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
|
level 1 cache
(foldoc) | primary cache
L1 cache
level 1 cache
level one cache
(L1 cache, level one cache) A small,
fast cache memory inside or close to the CPU chip.
For example, an Intel 80486 has an eight-kilobyte on-chip
cache, and most Pentiums have a 16-KB on-chip level one
cache that consists of an 8-KB instruction cache and an 8-KB
data cache.
The larger, slower secondary cache is normally connected to
the CPU via its external bus.
(1997-06-25)
|
level 2 cache
(foldoc) | secondary cache
L2 cache
level 2 cache
level two cache
second level cache
(Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
|
level one cache
(foldoc) | primary cache
L1 cache
level 1 cache
level one cache
(L1 cache, level one cache) A small,
fast cache memory inside or close to the CPU chip.
For example, an Intel 80486 has an eight-kilobyte on-chip
cache, and most Pentiums have a 16-KB on-chip level one
cache that consists of an 8-KB instruction cache and an 8-KB
data cache.
The larger, slower secondary cache is normally connected to
the CPU via its external bus.
(1997-06-25)
|
level two cache
(foldoc) | secondary cache
L2 cache
level 2 cache
level two cache
second level cache
(Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
|
pb cache
(foldoc) | Pipeline Burst Cache
PB Cache
Pipelined Burst Cache
(PB Cache) A synchronous cache built
from pipelined SRAM.
A cache in which reading or writing a new location takes
multiple cycles but subsequent locations can be accessed in
a single cycle. On Pentium systems in 1996, pipeline burst
caches are frequently used as secondary caches. The first 8
bytes of data are transferred in 3 CPU cycles, and the
next 3 8-byte pieces of data are transferred in one cycle
each.
(1996-10-13)
|
pipeline burst cache
(foldoc) | Pipeline Burst Cache
PB Cache
Pipelined Burst Cache
(PB Cache) A synchronous cache built
from pipelined SRAM.
A cache in which reading or writing a new location takes
multiple cycles but subsequent locations can be accessed in
a single cycle. On Pentium systems in 1996, pipeline burst
caches are frequently used as secondary caches. The first 8
bytes of data are transferred in 3 CPU cycles, and the
next 3 8-byte pieces of data are transferred in one cycle
each.
(1996-10-13)
|
pipelined burst cache
(foldoc) | Pipeline Burst Cache
PB Cache
Pipelined Burst Cache
(PB Cache) A synchronous cache built
from pipelined SRAM.
A cache in which reading or writing a new location takes
multiple cycles but subsequent locations can be accessed in
a single cycle. On Pentium systems in 1996, pipeline burst
caches are frequently used as secondary caches. The first 8
bytes of data are transferred in 3 CPU cycles, and the
next 3 8-byte pieces of data are transferred in one cycle
each.
(1996-10-13)
|
primary cache
(foldoc) | primary cache
L1 cache
level 1 cache
level one cache
(L1 cache, level one cache) A small,
fast cache memory inside or close to the CPU chip.
For example, an Intel 80486 has an eight-kilobyte on-chip
cache, and most Pentiums have a 16-KB on-chip level one
cache that consists of an 8-KB instruction cache and an 8-KB
data cache.
The larger, slower secondary cache is normally connected to
the CPU via its external bus.
(1997-06-25)
|
second level cache
(foldoc) | secondary cache
L2 cache
level 2 cache
level two cache
second level cache
(Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
|
secondary cache
(foldoc) | secondary cache
L2 cache
level 2 cache
level two cache
second level cache
(Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
|
set associative cache
(foldoc) | set associative cache
A compromise between a direct mapped cache
and a fully associative cache where each address is mapped
to a certain set of cache locations. The address space is
divided into blocks of 2^m bytes (the cache line size),
discarding the bottom m address bits. An "n-way set
associative" cache with S sets has n cache locations in each
set. Block b is mapped to set "b mod S" and may be stored in
any of the n locations in that set with its upper address bits
as a tag. To determine whether block b is in the cache, set
"b mod S" is searched associatively for the tag.
A direct mapped cache could be described as "one-way set
associative", i.e. one location in each set whereas a fully
associative cache is N-way associative (where N is the total
number of blocks in the cache). Performance studies have
shown that it is generally more effective to increase the
number of entries rather than associativity and that 2- to
16-way set associative caches perform almost as well as fully
associative caches at little extra cost over direct mapping.
(2004-10-18)
|
victim cache
(foldoc) | victim cache
An extension to a direct mapped cache that
adds a small, secondary, fully associative cache to store
cache blocks that have been ejected from the main cache due to
a capacity or conflict miss. These ejected blocks are likely
to be needed again so storing them in the secondary cache
should increase performance.
Victim caches with as few as five places have been found to
reduce conflict misses, especially for small, direct-mapped
data caches. E.g. a four-place victim cache removed 20% to
95% (depending on program) of such misses in a 4-KB cache.
(http://www.scism.sbu.ac.uk/ccsv/josephmb/CS-L2-MT/week12.html).
(2007-02-23)
|
virtual cache
(foldoc) | virtual cache
A cache which uses virtual address, i.e. it is between the
processor and the memory management unit. A virtual cache
cannot recognise external access to physical address, e.g. from
DMA. The whole cache must be flushed when swapping between
tasks which share same virtual address space.
(1994-11-30)
|
|