| podobné slovo | definícia |
complex instruction set computer
(encz) | complex instruction set computer, n: |
complex instruction set computing
(encz) | complex instruction set computing, n: |
reduced instruction set computer
(encz) | reduced instruction set computer, n: |
reduced instruction set computing
(encz) | reduced instruction set computing, n: |
complex instruction set computer
(wn) | complex instruction set computer
n 1: (computer science) a kind of computer architecture that has
a large number of instructions hard coded into the CPU chip
[syn: complex instruction set computing, {complex
instruction set computer}, CISC] [ant: RISC, {reduced
instruction set computer}, {reduced instruction set
computing}] |
complex instruction set computing
(wn) | complex instruction set computing
n 1: (computer science) a kind of computer architecture that has
a large number of instructions hard coded into the CPU chip
[syn: complex instruction set computing, {complex
instruction set computer}, CISC] [ant: RISC, {reduced
instruction set computer}, {reduced instruction set
computing}] |
reduced instruction set computer
(wn) | reduced instruction set computer
n 1: (computer science) a kind of computer architecture that has
a relatively small set of computer instructions that it can
perform [syn: reduced instruction set computing, {reduced
instruction set computer}, RISC] [ant: CISC, {complex
instruction set computer}, {complex instruction set
computing}] |
reduced instruction set computing
(wn) | reduced instruction set computing
n 1: (computer science) a kind of computer architecture that has
a relatively small set of computer instructions that it can
perform [syn: reduced instruction set computing, {reduced
instruction set computer}, RISC] [ant: CISC, {complex
instruction set computer}, {complex instruction set
computing}] |
complex instruction set computer
(foldoc) | Complex Instruction Set Computer
CISC
(CISC) A processor where each instruction can perform several
low-level operations such as memory access, arithmetic
operations or address calculations. The term was coined in
contrast to Reduced Instruction Set Computer.
Before the first RISC processors were designed, many computer
architects were trying to bridge the "semantic gap" - to
design instruction sets to support high-level languages by
providing "high-level" instructions such as procedure call and
return, loop instructions such as "decrement and branch if
non-zero" and complex addressing modes to allow data
structure and array accesses to be compiled into single
instructions.
While these architectures achieved their aim of allowing
high-level language constructs to be expressed in fewer
instructions, it was observed that they did not always result
in improved performance. For example, on one processor it was
discovered that it was possible to improve the performance by
NOT using the procedure call instruction but using a sequence
of simpler instructions instead. Furthermore, the more
complex the instruction set, the greater the overhead of
decoding an instruction, both in execution time and silicon
area. This is particularly true for processors which used
microcode to decode the (macro) instruction. It is easier
to debug a complex instruction set implemented in microcode
than one whose decoding is "hard-wired" in silicon.
Examples of CISC processors are the Motorola 680x0 family
and the Intel 80186 through Intel 486 and Pentium.
(1994-10-10)
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idealized instruction set
(foldoc) | Idealized Instruction Set
(IIS) The assembly language for the Flagship
parallel machine.
["An Idealized Instruction Set for a Packet Rewrite Machine",
J. Sargeant, Manchester U, 1988].
(1994-11-07)
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instruction set architecture
(foldoc) | instruction set architecture
(ISA) The parts of a processor's design that
need to be understood in order to write assembly language,
such as the machine language instructions and registers.
Parts of the architecture that are left to the implementation,
such as number of superscalar functional units, cache
size and cycle speed, are not part of the ISA.
The definition of SPARC, for example, carefully
distinguishes between an implementation and a specification.
(1999-01-16)
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instruction set processor
(foldoc) | Instruction Set Processor
(ISP) A family of languages for describing the
instruction sets of computers.
["Computer Structures: Readings and Examples", D.P. Siewiorek
et al, McGraw-Hill 1982].
(1995-10-12)
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orthogonal instruction set
(foldoc) | orthogonal instruction set
An instruction set where all (or most)
instructions have the same format and all registers and
addressing modes can be used interchangeably - the choices
of op code, register, and addressing mode are mutually
independent (loosely speaking, the choices are
"orthogonal"). This contrasts with some early Intel
microprocessors where only certain registers could be used
by certain instructions.
Examples include the PDP-11, 680x0, ARM, VAX.
(2002-06-26)
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reduced instruction set computer
(foldoc) | Reduced Instruction Set Computer
RISC
(RISC) A processor whose design is based on the
rapid execution of a sequence of simple instructions rather
than on the provision of a large variety of complex
instructions (as in a Complex Instruction Set Computer).
Features which are generally found in RISC designs are uniform
instruction encoding (e.g. the op-code is always in the same
bit positions in each instruction which is always one word
long), which allows faster decoding; a homogenous {register
set}, allowing any register to be used in any context and
simplifying compiler design; and simple addressing modes
with more complex modes replaced by sequences of simple
arithmetic instructions.
Examples of (more or less) RISC processors are the {Berkeley
RISC}, HP-PA, Clipper, i960, AMD 29000, MIPS R2000
and DEC Alpha. IBM's first RISC computer was the RT/PC
(IBM 801), they now produce the RISC-based {RISC
System/6000} and SP/2 lines.
Despite Apple Computer's bogus claims for their
PowerPC-based Macintoshes, the first RISC processor used
in a personal computer was the Advanced RISC Machine (ARM)
used in the Acorn Archimedes.
(1997-06-03)
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