| slovo | definícia |
powerpc
(foldoc) | PowerPC
PPC
(PPC) A RISC microprocessor designed
to meet a standard which was jointly designed by Motorola,
IBM, and Apple Computer (the PowerPC Alliance). The
PowerPC standard specifies a common {instruction set
architecture} (ISA), allowing anyone to design and fabricate
PowerPC processors, which will run the same code. The PowerPC
architecture is based on the IBM POWER architecture, used in
IBM's RS/6000 workstations. Currently IBM and
Motorola are working on PowerPC chips.
The PowerPC standard specifies both 32-bit and 64-bit data
paths. Early implementations were 32-bit (e.g. {PowerPC
601}); later higher-performance implementations were 64-bit
(e.g. PowerPC 620). A PowerPC has 32 integer registers (32-
or 64 bit) and 32 floating-point (IEEE standard 64 bit)
floating-point registers.
The POWER CPU chip and PowerPC have a (large) common core, but
both have instructions that the other doesn't. The PowerPC
offers the following features that POWER does not:
Support for running in little-endian mode.
Addition of single precision floating-point operations.
Control of branch prediction direction.
A hardware coherency model (not in Book I).
Some other floating-point instructions (some optional).
The real time clock (upper and lower) was replaced with the
time base registers (upper and lower), which don't count in
sec/ns (the decrementer also changed).
64-bit instruction operands, registers, etc. (in 64 bit
processors).
See also PowerOpen, PowerPC Platform (PReP).
{IBM PPC info
(http://fnctsrv0.chips.ibm.com/products/ppc/index.html)}.
(gopher://info.hed.apple.com/), "Apple Corporate News/"
(press releases), "Apple Technologies/" and "Product
Information/". (gopher://ike.engr.washington.edu/), "IBM
General News/", "IBM Product Announcements/", "IBM Detailed
Product Announcements/", "IBM Hardware Catalog/".
Usenet newsgroups: news:comp.sys.powerpc,
news:comp.sys.mac.hardware.
["Microprocessor Report", 16 October 1991].
(1994-09-30)
|
| | podobné slovo | definícia |
powerpc
(foldoc) | PowerPC
PPC
(PPC) A RISC microprocessor designed
to meet a standard which was jointly designed by Motorola,
IBM, and Apple Computer (the PowerPC Alliance). The
PowerPC standard specifies a common {instruction set
architecture} (ISA), allowing anyone to design and fabricate
PowerPC processors, which will run the same code. The PowerPC
architecture is based on the IBM POWER architecture, used in
IBM's RS/6000 workstations. Currently IBM and
Motorola are working on PowerPC chips.
The PowerPC standard specifies both 32-bit and 64-bit data
paths. Early implementations were 32-bit (e.g. {PowerPC
601}); later higher-performance implementations were 64-bit
(e.g. PowerPC 620). A PowerPC has 32 integer registers (32-
or 64 bit) and 32 floating-point (IEEE standard 64 bit)
floating-point registers.
The POWER CPU chip and PowerPC have a (large) common core, but
both have instructions that the other doesn't. The PowerPC
offers the following features that POWER does not:
Support for running in little-endian mode.
Addition of single precision floating-point operations.
Control of branch prediction direction.
A hardware coherency model (not in Book I).
Some other floating-point instructions (some optional).
The real time clock (upper and lower) was replaced with the
time base registers (upper and lower), which don't count in
sec/ns (the decrementer also changed).
64-bit instruction operands, registers, etc. (in 64 bit
processors).
See also PowerOpen, PowerPC Platform (PReP).
{IBM PPC info
(http://fnctsrv0.chips.ibm.com/products/ppc/index.html)}.
(gopher://info.hed.apple.com/), "Apple Corporate News/"
(press releases), "Apple Technologies/" and "Product
Information/". (gopher://ike.engr.washington.edu/), "IBM
General News/", "IBM Product Announcements/", "IBM Detailed
Product Announcements/", "IBM Hardware Catalog/".
Usenet newsgroups: news:comp.sys.powerpc,
news:comp.sys.mac.hardware.
["Microprocessor Report", 16 October 1991].
(1994-09-30)
|
powerpc 601
(foldoc) | PowerPC 601
A 32-bit RISC processor with 2.8 million
transistors (~1.2 million in the core logic) and 32 kilobytes
of on-chip cache. Die size: 118.8 mm2. Heat dissipation at
66MHz: 9W. Performance at 66MHz: integer >60 SPECint92,
floating-point >80 SPECfp92. Estimated manufacturing
cost: $76. Maximum instructions per cycle: 3. 32 32-bit
general-purpose registers. 32 64-bit floating-point
registers. Successors: PowerPC 603, 604, 620.
(2000-01-12)
|
powerpc g3
(foldoc) | PowerPC G3
A processor chip from Apple Computer, Inc..
Described by Apple as "the third generation in the development
of advanced processor technology" the first PowerPC G3
products were launched in 1997. It is specifically optimised
for the Macintosh Operating System and uses backside cache
to improve performance. The PowerPC G3 has been used by Apple
in notebook, desktop and server products.
(http://apple.com/powermac/technologies/g3.html).
(1998-10-03)
|
powerpc platform
(foldoc) | PowerPC Platform
CHRP
Common Hardware Reference Platform
PowerPC Reference Platform
PPCP
(PPCP, PReP - PowerPC Reference
Platform, formerly CHRP - Common Hardware Reference Platform)
An open system standard, designed by IBM, intended to ensure
compatibility among PowerPC-based systems built by different
companies. The PReP standard specifies the PCI bus, but
will also support ISA, MicroChannel and PCMCIA.
PReP-compliant systems will be able to run the Macintosh OS,
OS/2, WorkplaceOS, AIX, Solaris, Taligent and
Windows NT. IBM systems will (of course) be PReP-compliant.
Apple's first PowerPC Macintoshes will not be compliant,
but future ones may be.
{IBM info
(http://fnctsrv0.chips.ibm.com/products/ppc/L3ppcp.html)}.
(http://billboard.emedia.com.au/chipster/computers/CHRP/whatsCHRP.html).
[Current OS statuses?]
(1997-03-23)
|
powerpc reference platform
(foldoc) | PowerPC Platform
CHRP
Common Hardware Reference Platform
PowerPC Reference Platform
PPCP
(PPCP, PReP - PowerPC Reference
Platform, formerly CHRP - Common Hardware Reference Platform)
An open system standard, designed by IBM, intended to ensure
compatibility among PowerPC-based systems built by different
companies. The PReP standard specifies the PCI bus, but
will also support ISA, MicroChannel and PCMCIA.
PReP-compliant systems will be able to run the Macintosh OS,
OS/2, WorkplaceOS, AIX, Solaris, Taligent and
Windows NT. IBM systems will (of course) be PReP-compliant.
Apple's first PowerPC Macintoshes will not be compliant,
but future ones may be.
{IBM info
(http://fnctsrv0.chips.ibm.com/products/ppc/L3ppcp.html)}.
(http://billboard.emedia.com.au/chipster/computers/CHRP/whatsCHRP.html).
[Current OS statuses?]
(1997-03-23)
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