| slovo | definícia |
pipeline
(mass) | pipeline
- potrubie |
pipeline
(encz) | pipeline,plynovod n: Pavel Machek; Giza |
pipeline
(encz) | pipeline,potrubí n: Pajosh |
pipeline
(encz) | pipeline,ropovod n: Zdeněk Brož |
pipeline
(encz) | pipeline,zřetězení Stan |
pipeline
(gcide) | pipeline \pipeline\, pipe line \pipe line\
1. A line of pipe with pumping machinery and apparatus for
conveying liquids, gases, or finely divided solids, such
as petroleum or natural gas, between distant points.
[Webster 1913 Suppl. +PJC]
2. fig. an information channel direct from the source.
[PJC]
3. the set of stages and processes from the invention or
design of a product to its ultimate use, production, or
commercial sale. Used commonly in the phrase
in the pipeline, i. e. still in preparation or under
development.
[PJC] |
Pipe-line
(gcide) | Pipe-line \Pipe"-line`\, v. t.
To convey by a pipe line; to furnish with a pipe line or pipe
lines.
[Webster 1913 Suppl.] |
pipeline
(wn) | pipeline
n 1: gossip spread by spoken communication; "the news of their
affair was spread by word of mouth" [syn: grapevine,
pipeline, word of mouth]
2: a pipe used to transport liquids or gases; "a pipeline runs
from the wells to the seaport" [syn: pipeline, line] |
pipeline
(foldoc) | pipeline
pipelined
pipelining
A sequence of functional units ("stages")
which performs a task in several steps, like an assembly line
in a factory. Each functional unit takes inputs and produces
outputs which are stored in its output buffer. One stage's
output buffer is the next stage's input buffer. This
arrangement allows all the stages to work in parallel thus
giving greater throughput than if each input had to pass
through the whole pipeline before the next input could enter.
The costs are greater latency and complexity due to the need
to synchronise the stages in some way so that different inputs
do not interfere. The pipeline will only work at full
efficiency if it can be filled and emptied at the same rate
that it can process.
Pipelines may be synchronous or asynchronous. A synchronous
pipeline has a master clock and each stage must complete its
work within one cycle. The minimum clock period is thus
determined by the slowest stage. An asynchronous pipeline
requires handshaking between stages so that a new output is
not written to the interstage buffer before the previous one
has been used.
Many CPUs are arranged as one or more pipelines, with
different stages performing tasks such as fetch instruction,
decode instruction, fetch arguments, arithmetic operations,
store results. For maximum performance, these rely on a
continuous stream of instructions fetched from sequential
locations in memory. Pipelining is often combined with
instruction prefetch in an attempt to keep the pipeline
busy.
When a branch is taken, the contents of early stages will
contain instructions from locations after the branch which
should not be executed. The pipeline then has to be flushed
and reloaded. This is known as a pipeline break.
(1996-10-13)
|
| | podobné slovo | definícia |
aeration pipeline
(encz) | aeration pipeline,zavzdušňovací potrubí [eko.] RNDr. Pavel Piskač |
in the pipeline
(encz) | in the pipeline,v plánu jose |
oil pipeline
(encz) | oil pipeline, n: |
pipeline company
(encz) | pipeline company, n: |
pipelined
(encz) | pipelined, |
pipelines
(encz) | pipelines,potrubí n: pl. |
riser pipeline
(encz) | riser pipeline, n: |
trans-alaska pipeline
(encz) | trans-Alaska pipeline, n: |
in the pipeline
(gcide) | pipeline \pipeline\, pipe line \pipe line\
1. A line of pipe with pumping machinery and apparatus for
conveying liquids, gases, or finely divided solids, such
as petroleum or natural gas, between distant points.
[Webster 1913 Suppl. +PJC]
2. fig. an information channel direct from the source.
[PJC]
3. the set of stages and processes from the invention or
design of a product to its ultimate use, production, or
commercial sale. Used commonly in the phrase
in the pipeline, i. e. still in preparation or under
development.
[PJC] |
Pipe-line
(gcide) | pipeline \pipeline\, pipe line \pipe line\
1. A line of pipe with pumping machinery and apparatus for
conveying liquids, gases, or finely divided solids, such
as petroleum or natural gas, between distant points.
[Webster 1913 Suppl. +PJC]
2. fig. an information channel direct from the source.
[PJC]
3. the set of stages and processes from the invention or
design of a product to its ultimate use, production, or
commercial sale. Used commonly in the phrase
in the pipeline, i. e. still in preparation or under
development.
[PJC]Pipe-line \Pipe"-line`\, v. t.
To convey by a pipe line; to furnish with a pipe line or pipe
lines.
[Webster 1913 Suppl.] |
alaskan pipeline
(wn) | Alaskan pipeline
n 1: an oil pipeline that runs 800 miles from wells at Prudhoe
Bay to the port of Valdez [syn: Alaskan pipeline, {trans-
Alaska pipeline}] |
oil pipeline
(wn) | oil pipeline
n 1: a pipeline used to transport oil |
pipeline company
(wn) | pipeline company
n 1: a company that operates oil pipelines for the oil industry |
riser pipeline
(wn) | riser pipeline
n 1: a vertical pipe in a building [syn: riser, riser pipe,
riser pipeline, riser main] |
trans-alaska pipeline
(wn) | trans-Alaska pipeline
n 1: an oil pipeline that runs 800 miles from wells at Prudhoe
Bay to the port of Valdez [syn: Alaskan pipeline, {trans-
Alaska pipeline}] |
microprocessor without interlocked pipeline stages
(foldoc) | Microprocessor without Interlocked Pipeline Stages
MIPS project
(MIPS) A project at Stanford University intended
to simplify processor design by eliminating hardware
interlocks between the five pipeline stages. This means
that only single execution cycle instructions can access the
thirty two 32-bit general registers, so that the compiler
can schedule them to avoid conflicts. This also means that
LOAD/STORE and branch instructions have a one-cycle delay to
account for. However, because of the importance of multiply
and divide instructions, a special HI/LO pair of
multiply/divide registers exist which do have hardware
interlocks, since these take several cycles to execute and
complicate instruction scheduling.
The project eventually lead to the commercial MIPS R2000
processor.
(1995-02-09)
|
pipeline break
(foldoc) | pipeline break
pipeline stall
(Or "pipeline stall") The delay caused on a
processor using pipelines when a transfer of control is
taken. Normally when a control-transfer instruction (a
branch, conditional branch, call or trap) is taken, any
following instructions which have been loaded into the
processor's pipeline must be discarded or "flushed" and new
instructions loaded from the branch destination. This
introduces a delay before the processor can resume execution.
"Delayed control-transfer" is a technique used to reduce
this effect.
(1996-10-13)
|
pipeline burst cache
(foldoc) | Pipeline Burst Cache
PB Cache
Pipelined Burst Cache
(PB Cache) A synchronous cache built
from pipelined SRAM.
A cache in which reading or writing a new location takes
multiple cycles but subsequent locations can be accessed in
a single cycle. On Pentium systems in 1996, pipeline burst
caches are frequently used as secondary caches. The first 8
bytes of data are transferred in 3 CPU cycles, and the
next 3 8-byte pieces of data are transferred in one cycle
each.
(1996-10-13)
|
pipeline stall
(foldoc) | pipeline break
pipeline stall
(Or "pipeline stall") The delay caused on a
processor using pipelines when a transfer of control is
taken. Normally when a control-transfer instruction (a
branch, conditional branch, call or trap) is taken, any
following instructions which have been loaded into the
processor's pipeline must be discarded or "flushed" and new
instructions loaded from the branch destination. This
introduces a delay before the processor can resume execution.
"Delayed control-transfer" is a technique used to reduce
this effect.
(1996-10-13)
|
pipelined
(foldoc) | pipeline
pipelined
pipelining
A sequence of functional units ("stages")
which performs a task in several steps, like an assembly line
in a factory. Each functional unit takes inputs and produces
outputs which are stored in its output buffer. One stage's
output buffer is the next stage's input buffer. This
arrangement allows all the stages to work in parallel thus
giving greater throughput than if each input had to pass
through the whole pipeline before the next input could enter.
The costs are greater latency and complexity due to the need
to synchronise the stages in some way so that different inputs
do not interfere. The pipeline will only work at full
efficiency if it can be filled and emptied at the same rate
that it can process.
Pipelines may be synchronous or asynchronous. A synchronous
pipeline has a master clock and each stage must complete its
work within one cycle. The minimum clock period is thus
determined by the slowest stage. An asynchronous pipeline
requires handshaking between stages so that a new output is
not written to the interstage buffer before the previous one
has been used.
Many CPUs are arranged as one or more pipelines, with
different stages performing tasks such as fetch instruction,
decode instruction, fetch arguments, arithmetic operations,
store results. For maximum performance, these rely on a
continuous stream of instructions fetched from sequential
locations in memory. Pipelining is often combined with
instruction prefetch in an attempt to keep the pipeline
busy.
When a branch is taken, the contents of early stages will
contain instructions from locations after the branch which
should not be executed. The pipeline then has to be flushed
and reloaded. This is known as a pipeline break.
(1996-10-13)
|
pipelined burst cache
(foldoc) | Pipeline Burst Cache
PB Cache
Pipelined Burst Cache
(PB Cache) A synchronous cache built
from pipelined SRAM.
A cache in which reading or writing a new location takes
multiple cycles but subsequent locations can be accessed in
a single cycle. On Pentium systems in 1996, pipeline burst
caches are frequently used as secondary caches. The first 8
bytes of data are transferred in 3 CPU cycles, and the
next 3 8-byte pieces of data are transferred in one cycle
each.
(1996-10-13)
|
superpipelined
(foldoc) | superpipelined
1. Traditional pipelined architectures have a single
pipeline stage for each of: instruction fetch, instruction
decode, memory read, ALU operation and memory write. A
superpipelined processor has a pipeline where each of
these logical steps may be subdivided into multiple pipeline
stages.
2. Marketese for pipelined.
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